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70V631S12BFGI Datasheet(PDF) 1 Page - Integrated Device Technology |
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70V631S12BFGI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 23 page  ©2013 Integrated Device Technology, Inc. 1 OCTOBER 2013 DSC-5622/7 Functional Block Diagram ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ Separate byte controls for multiplexed bus and bus matching compatibility ◆ ◆ ◆ ◆ ◆ Supports JTAG features compliant to IEEE 1149.1 – Due to limited pin count, JTAG is not supported on the 128-pin TQFP package. ◆ ◆ ◆ ◆ ◆ LVTTL-compatible, single 3.3V (±150mV) power supply for core ◆ ◆ ◆ ◆ ◆ LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port ◆ ◆ ◆ ◆ ◆ Available in a 128-pin Thin Quad Flatpack, 208-ball fine pitch Ball Grid Array, and 256-ball Ball Grid Array ◆ ◆ ◆ ◆ ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ ◆ ◆ ◆ ◆ Green parts available, see ordering information Features ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 10/12/15ns (max.) – Industrial: 12ns (max.) ◆ ◆ ◆ ◆ ◆ Dual chip enables allow for depth expansion without external logic ◆ ◆ ◆ ◆ ◆ IDT70V631 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave ◆ ◆ ◆ ◆ ◆ Busy and Interrupt Flags ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM IDT70V631S NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). CE0R R/ WR CE1R LBR UBR 256K x 18 MEMORY ARRAY Address Decoder A17R A0R Address Decoder CE0L R/ WL CE1L LBL UBL Dout0-8_L Dout9-17_L Dout0-8_R Dout9-17_R B E 0 L B E 1 L B E 1 R B E 0 R I/O0L- I/O17L I/O0R -I/O17R Din_L ADDR_L Din_R ADDR_R OER OEL ARBITRATION INTERRUPT SEMAPHORE LOGIC SEML INTL BUSYL M/ S R/ WL OEL R/ WR OER BUSYR SEMR INTR CE0L CE1L CE0R CE1R TMS TCK TRST TDI TDO JTAG 5622 drw 01 A17L A0L |
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