IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

10

NOTE:

1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.

Figure 8. Full Flag Timing

NOTE:

The Latency Timings apply only at the Empty Boundary (EF = LOW).

Figure 9. Empty Flag Timing

NEXT DATA READ

DATA READ

WCLK

FF

WEN1

WEN2

(If Applicable)

RCLK

REN1,

REN2

DATA IN OUTPUT REGISTER

OE LOW

NO WRITE

NO WRITE

4092 drw10

(1)

(1)

NO WRITE

DATA WRITE 1

DATA WRITE 2

WCLK

RCLK

EF

REN1,

REN2

OE

DATA READ

(1)

DATA IN OUTPUT REGISTER

(1)

LOW

WEN2

(If Applicable)

WEN1

4092 drw11