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7014S25JGI8 Datasheet(PDF) 8 Page - Integrated Device Technology

Part # 7014S25JGI8
Description  HIGH-SPEED 4K x 9DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

7014S25JGI8 Datasheet(HTML) 8 Page - Integrated Device Technology

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IDT7014S
High-Speed 4K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
8
Truth Table I – Read/Write Control
Timing Waveform of Write Cycle(1,2,3,4,5)
Functional Description
The IDT7014 provides two ports with separate control, address,
and I/O pins that permit independent access for reads or writes to
any location in memory. It lacks the chip enable feature of CMOS Dual
Ports,thusitoperatesinactivemodeassoonaspowerisapplied.Each
porthasitsownOutputEnablecontrol(OE).Inthereadmode,theport’s
OEturnsontheoutputdriverswhensetLOW. Theuserapplicationshould
avoidsimultaneouswriteoperationstothesamememorylocation.There
isnoon-chiparbitrationcircuitrytoresolvewritepriorityandpartialdata
frombothportsmaybewritten.READ/WRITEconditionsareillustrated
in Table 1.
NOTE:
1. AOL - A11L is not equal to AOR - A11R.
'H' = HIGH,'L' = LOW, 'X' = Don’t Care, and 'Z' = HIGH Impedance.
2528 drw 10
R/
W
tWP
tDW
DATAOUT
ADDRESS
DATAIN
OE
tAW
tAS
(5)
tWR
tDH
tOW
tHZ
(4)
(3)
(3)
tWZ (4)
Left or Right Port(1)
R/
WOE
D0-8
Function
LXDATAIN
Data written into memory
HL
DATAOUT
Data in memory output on port
X
H
Z
High-impedance outputs
2528 tbl 10
NOTES:
1. R/W must be HIGH during all address transitions.
2. tWR is measured from R/W going HIGH to the end of write cycle.
3. During this period, the I/O pins are in the output state, and input signals must not be applied.
4. Transition is measured 0mV from the Low or High-impedance voltage with the Output Test Load (Figure 2).
5. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.


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