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72V36110L10PFGI Datasheet(PDF) 4 Page - Integrated Device Technology |
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72V36110L10PFGI Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 48 page  4 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO 65,536 x 36 and 131,072 x 36 DESCRIPTION (CONTINUED) Figure 1. Single Device Configuration Signal Flow Diagram operation,whichconsistsofactivatingRENandenablingarisingRCLKedge, willshiftthewordfrominternalmemorytothedataoutputlines. In FWFT mode, the first word written to an empty FIFO is clocked directly tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.A RENdoes not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse. For applications requiring more data storage capacity than a single FIFO canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespectiveoftimingmode. PAE and PAFcanbeprogrammedindependentlytoswitchatanypointin memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations from the empty boundary and the PAF threshold can also be set at similar predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring Master Reset by the state of the FSEL0, FSEL1, and LD pins. For serial programming, SEN together with LD on each rising edge of WCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused to load the offset registers via Dn. REN together with LD on each rising edge ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether serialorparalleloffsetloadinghasbeenselected. DuringMasterReset(MRS)thefollowingeventsoccur: thereadandwrite pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation, whenreprogrammingprogrammableflagswouldbeundesirable. ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost- Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modescanbesettobeeitherasynchronousorsynchronousforthe PAEand PAFflags. BUS- MATCHING (BM) (x36, x18 or x9) DATA OUT (Q0 - Qn) (x36, x18 or x9) DATA IN (D0 - Dn) MASTER RESET ( MRS) READ CLOCK (RCLK/RD*) READ ENABLE ( REN) OUTPUT ENABLE ( OE) EMPTY FLAG/OUTPUT READY ( EF/OR) PROGRAMMABLE ALMOST-EMPTY ( PAE) WRITE CLOCK (WCLK/WR*) WRITE ENABLE ( WEN) LOAD ( LD) FULL FLAG/INPUT READY ( FF/IR) PROGRAMMABLE ALMOST-FULL ( PAF) IDT 72V36100 72V36110 PARTIAL RESET ( PRS) FIRST WORD FALL THROUGH/ SERIAL INPUT (FWFT/SI) RETRANSMIT ( RT) 6117 drw03 HALF-FULL FLAG ( HF) SERIAL ENABLE( SEN) INPUT WIDTH (IW) OUTPUT WIDTH (OW) BIG-ENDIAN/LITTLE-ENDIAN ( BE) INTERSPERSED/ NON-INTERSPERSED PARITY (IP) |
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