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72V265LA20TFG Datasheet(PDF) 3 Page - Integrated Device Technology |
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72V265LA20TFG Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 27 page  3 IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES DESCRIPTION (CONTINUED) Figure 1. Block Diagram of Single 8,192 x 18 and 16,384 x 18 Synchronous FIFO DATA OUT (Q0 - Qn) DATA IN (D0 - Dn) MASTER RESET (MRS) READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) EMPTY FLAG/OUTPUT READY (EF/OR) PROGRAMMABLE ALMOST-EMPTY (PAE) WRITE CLOCK (WCLK) WRITE ENABLE (WEN) LOAD (LD) FULL FLAG/INPUT READY (FF/IR) PROGRAMMABLE ALMOST-FULL (PAF) IDT 72V255LA 72V265LA PARTIAL RESET (PRS) FIRST WORD FALL THROUGH/SERIAL INPUT (FWFT/SI) RETRANSMIT (RT) 4672 drw 03 HALF FULL FLAG (HF) SERIAL ENABLE(SEN) Therearetwopossibletimingmodesofoperationwiththesedevices:IDT Standard mode and First Word Fall Through (FWFT) mode. InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread operation,whichconsistsofactivatingRENandenablingarisingRCLKedge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly tothedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoes not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF /IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EFand FF functions are selected in IDT Standard mode. The IR and OR functions areselectedinFWFTmode. HF,PAE andPAFarealwaysavailableforuse, irrespectiveoftimingmode. PAE and PAF can be programmed independently to switch at any point in memory. (SeeTableIandTableII.) Programmableoffsetsdeterminetheflag switchingthresholdandcanbeloadedbytwomethods:parallelorserial. Two defaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchat127 or1,023locationsfromtheemptyboundaryandthePAFthresholdcanbeset at127or1,023locationsfromthefullboundary. Thesechoicesaremadewith the LD pin during Master Reset. For serial programming, SEN together with LD on each rising edge of WCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused to load the offset registers via Dn. REN togetherwith LD oneachrisingedge of RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected. DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite pointers are set to the first location of the FIFO. The FWFT pin selects IDT StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023 withserialprogramming. Theflagsareupdatedaccordingtothetimingmode anddefaultoffsetsselected. The Partial Reset (PRS) also sets the read and write pointers to the first locationofthememory. However,thetimingmode,partialflagprogramming method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset remainunchanged.Theflagsareupdatedaccordingtothetimingmodeand offsets in effect. PRS is useful for resetting a device in mid-operation, when reprogramming partial flags would be undesirable. TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit operationbysettingthereadpointertothefirstlocationofthememoryarray. If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol inputs) will immediately take the device out of the power down state. The IDT72V255LA/72V265LA are fabricated using IDT’s high speed submicron CMOS technology. |
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