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72V801L15TFG8 Datasheet(PDF) 10 Page - Integrated Device Technology |
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72V801L15TFG8 Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 16 page 10 IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Figure 6. Read Cycle Timing NOTE: 1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW). Figure 7. First Data Word Latency Timing NOTE: 1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB) edge. tENH tENS NO OPERATION tOLZ VALID DATA tSKEW1 (1) tCLK tCLKH tCLKL tREF tREF tA tOE tOHZ RCLKA (RCLKB) RENA1, RENA2 ( RENB1, RENB2) EFA (EFB) QA0 - QA8 (QB0 - QB8) OEA (OEB) WCLKA, WCLKB WENA1 (WENB1) WENA2 (WENB2) 4093 drw 08 tDS D0 (First Valid tSKEW1 D0 D1 D3 D2 D1 tENS tFRL (1) tREF tA tOLZ tOE tA WCLKA (WCLKB) DA0 - DA8 (DB0 - DB8) WENA2 (WENB2) (If Applicable) RCLKA (RCLKB) EFA (EFB) RENA1, RENA2 ( RENB1, RENB2) QA0 - QA8 (QB0 - QB8) OEA (OEB) WENA1 ( WENB1) 4093 drw 09 tENS tENS |
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