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7015L15PFG8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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7015L15PFG8 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 21 page 1 ©2016 Integrated Device Technology, Inc. MARCH 2016 DSC 2954/11 I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/ WL CEL OEL BUSYL A12L A0L 2954 drw 01 I/O0L- I/O8L CEL OEL R/ WL SEML INTL M/ S BUSYR I/O0R-I/O8R A12R A0R SEMR INTR CER OER (2) (1,2) (1,2) (2) R/ WR CER OER R/ WR 13 13 Functional Block Diagram ◆ M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave ◆ Busy and Interrupt Flag ◆ On-chip port arbitration logic ◆ Full on-chip hardware support of semaphore signaling between ports ◆ Fully asynchronous operation from either port ◆ TTL-compatible, single 5V (±10%) power supply ◆ Available in 68-pin PLCC and an 80-pin TQFP ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Green parts available, see ordering information Features: ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access – Commercial:12/15/17/20/25/35ns(max.) – Industrial:20ns(max.) ◆ Low-power operation – IDT7015S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7015L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ IDT7015 easily expands data bus width to 18 bits or more using the Master/Slave select when cascading more than onedevice HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM IDT7015S/L NOTES: 1. In MASTER mode: BUSY is an output and is a push-pull driver In SLAVE mode: BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull drivers. |
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