1

MARCH 2013

IDT72V205, IDT72V215,

IDT72V225, IDT72V235,

IDT72V245

IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

DSC-4294/7

256 x 18, 512 x 18, 1,024 x 18,

2,048 x 18, and 4,096 x 18

FEATURES:

and Almost-Full flags with default settings

FUNCTIONAL BLOCK DIAGRAM

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY

256 x 18, 512 x 18

1,024 x 18, 2,048 x 18

4,096 x 18

OFFSET REGISTER

FLAG

LOGIC

FF/IR

PAF

EF/OR

PAE

HF/(WXO)

READ POINTER

READ CONTROL

LOGIC

WRITE CONTROL

LOGIC

WRITE POINTER

EXPANSION LOGIC

RESET LOGIC

WEN

WCLK

D0-D17

LD

RS

(

HF)/WXO

WXI

REN

RCLK

OE

Q0-Q17

RXO

RXI

FL

4294 drw 01

°°°°°C to +85°°°°°C) is available

DESCRIPTION:

TheIDT72V205/72V215/72V225/72V235/72V245arefunctionallycom-

patibleversionsoftheIDT72205LB/72215LB/72225LB/72235LB/72245LB,

designed to run off a 3.3V supply for exceptionally low power consumption.

These devices are very high-speed, low-power First-In, First-Out (FIFO)

memories with clocked read and write controls. These FIFOs are applicable

forawidevarietyofdatabufferingneeds,suchasopticaldiskcontrollers,Local

AreaNetworks(LANs),andinterprocessorcommunication.

TheseFIFOshave18-bitinputandoutputports. Theinputportiscontrolled

byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataisread

intothesynchronousFIFOoneveryclockwhenWENisasserted.Theoutput

portiscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).

TheReadClock(RCLK)canbetiedtotheWriteClockforsingleclockoperation

orthetwoclockscanrunasynchronousofoneanotherfordual-clockoperation.

AnOutputEnablepin(OE)isprovidedonthereadportforthree-statecontrol

oftheoutput.