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72V811L10TFGI Datasheet(PDF) 3 Page - Integrated Device Technology |
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72V811L10TFGI Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 16 page 3 IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTIONS TheIDT72V801/72V811/72V821/72V831/72V841/72V851'stwoFIFOs, referredtoasFIFOAandFIFOB,areidenticalineveryrespect.Thefollowing descriptiondefinestheinputandoutputsignalsforFIFOA.Thecorresponding signal names for FIFO B are provided in parentheses. Symbol Name I/O Description DA0-DA8 A Data Inputs I 9-bit data inputs to RAM array A. DB0-DB8 B Data Inputs I 9-bit data inputs to RAM array B. RSA, RSB Reset I When RSA(RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go LOW. After power- up, a reset of both FIFOs A and B is required before an initial WRITE. WCLKA Write Clock I Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write enable(s) WCLKB areasserted. WENA1 Write Enable 1 I If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only write enable pin that can be WENB1 used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into the FIFO. Data will not be written into the FIFO if FFA (FFB) is LOW. WENA2/LDA Write Enable 2/ I FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB) is HIGH at WENB2/LDB Load reset, this pin operates as a second Write Enable. If WENA2/LDA (WENB2/LDB) is LOW at reset this pin operates as a control to load and read the programmable flag offsets for its respective array. If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into FIFO A (B). Data will not be written into FIFO A (B) if FFA (FFB) is LOW. If the FIFO is configured to have programmable flags, LDA(LDB) is held LOW to write or read the programmable flag offsets. QA0-QA8 A Data Outputs O 9-bit data outputs from RAM array A. QB0-QB8 B Data Outputs O 9-bit data outputs from RAM array B. RCLKA Read Clock I Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1(RENB1) and RCLKB RENA2 (RENB2) are asserted. RENA1 Read Enable 1 I When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every LOW-to-HIGH RENB1 transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW. RENA2 Read Enable 2 I When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every LOW-to- RENB2 HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW. OEA OutputEnable I When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the OEB outputs DA0- DA8 (DB0-DB8) will be in a high-impedance state. EFA Empty Flag O When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. When EFA EFB (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB). PAEA Programmable O When PAEA(PAEB) is LOW, FIFO A (B) is Almost-Empty based on the offset programmed into the appropriate PAEB Almost-Empty Flag offset register. The default offset at reset is Empty+7. PAEA (PAEB) is synchronized to RCLKA (RCLKB). PAFA Programmable O When PAFA(PAFB) is LOW, FIFO A (B) is Almost-Full based on the offset programmed into the appropriate offset PAFB Almost-FullFlag register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB). FFA Full Flag O When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. When FFA (FFB) is FFB HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB). VCC Power +3.3V power supply pin. GND Ground 0V ground pin. |
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