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70V06L25PFGI Datasheet(PDF) 9 Page - Integrated Device Technology |
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70V06L25PFGI Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 23 page 6.42 IDT70V06S/L High-Speed 3.3V 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 9 Waveform of Read Cycles(5) NOTES: 1. Timing depends on which signal is asserted las OE or CE. 2. Timing depends on which signal is de-asserted first CE or OE. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH. tRC R/ W CE ADDR tAA OE 2942 drw 07 (4) tACE (4) tAOE (4) (1) tLZ tOH (2) tHZ (3,4) tBDD DATAOUT BUSYOUT VALID DATA (4) |
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