9

256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

MARCH 2013

Figure 2. Writing to Offset Registers

LD

WEN

WCLK

Selection

0

0

Writingtooffsetregisters:

EmptyOffset

FullOffset

0

1

NoOperation

1

0

Write Into FIFO

1

1

NoOperation

Figure 3. Offset Register Location and Default Values

SIGNAL DESCRIPTIONS:

INPUTS:

Data inputs for 18-bit wide data.

CONTROLS:

RESET (RS)

Reset is accomplished whenever the Reset (RS) input is taken to a LOW

state. During reset, both internal read and write pointers are set to the first

location. A reset is required after power-up before a write operation can take

place.TheHalf-FullFlag(HF)andProgrammableAlmost-FullFlag(PAF)will

Flag(EF)willresettoLOWinIDTStandardmodebutwillresettoHIGHinFWFT

mode. Duringreset,theoutputregisterisinitializedtoallzerosandtheoffset

registersareinitializedtotheirdefaultvalues.

WRITE CLOCK (WCLK)

AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock

(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH

transitionofWCLK.

The Write and Read Clocks can be asynchronous or coincident.

WRITE ENABLE (WEN)

WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray

on the rising edge of every WCLK cycle if the device is not full. Data is stored

in the RAM array sequentially and independently of any ongoing read

operation.

WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK

cycle.

To prevent data overflow in the IDT Standard Mode, FF will go LOW,

inhibiting further write operations. Upon the completion of a valid read cycle,

FF will go HIGH allowing a write to occur. TheFF flag is updated on the rising

edgeofWCLK.

To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting

further write operations. Upon the completion of a valid read cycle, IR will go

LOWallowingawritetooccur. TheIRflagisupdatedontherisingedgeofWCLK.

WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.

READ CLOCK (RCLK)

DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead

Clock (RCLK), when Output Enable (OE) is set LOW.

The Write and Read Clocks can be asynchronous or coincident.

READ ENABLE (REN)

WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput

register on the rising edge of every RCLK cycle if the device is not empty.

WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdataand

the previous data value.

wordwrittentoanemptyFIFO,mustberequestedusingREN. Whenthelast

wordhasbeenreadfromtheFIFO,theEmptyFlag(EF)willgoLOW,inhibiting

furtherreadoperations. RENisignoredwhentheFIFOisempty. Onceawrite

isperformed,EFwillgoHIGHallowingareadtooccur. TheEFflagisupdated

on the rising edge of RCLK.

IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes

afterthefirstwrite. RENdoesnotneedtobeassertedLOW. Inordertoaccess

allotherwords,areadmustbeexecutedusingREN. TheRCLKLOWtoHIGH

transitionafterthelastwordhasbeenreadfromtheFIFO,OutputReady(OR)

willgoHIGHwithatrue read(RCLKwith REN=LOW),inhibitingfurtherread

operations. REN is ignored when the FIFO is empty.

OUTPUT ENABLE (OE)

When Output Enable (OE) is enabled (LOW), the parallel output buffers

receivedatafromtheoutputregister.WhenOEisdisabled(HIGH),theQoutput

databusisinahigh-impedancestate.

LOAD (LD)

The IDT72V205/72V215/72V225/72V235/72V245 devices contain two

12-bitoffsetregisterswithdataontheinputs,orreadontheoutputs. Whenthe

Load (LD) pin is set LOW and WEN is set LOW, data on the inputs D0-D11 is

writtenintotheEmptyOffsetregisteronthefirstLOW-to-HIGHtransitionofthe

Write Clock (WCLK). When the LD pin and WEN are held LOW then data is

written into the Full Offset register on the second LOW-to-HIGH transition of

WCLK.ThethirdtransitionofWCLKagainwritestotheEmptyOffsetregister.

However,writingalloffsetregistersdoesnothavetooccuratonetime.One

ortwooffsetregisterscanbewrittenandthenbybringingtheLDpinHIGH,the

FIFOisreturnedtonormalread/writeoperation.WhentheLDpinissetLOW,

and WEN is LOW, the next offset register in sequence is written.

EMPTY OFFSET REGISTER

17

11

0

001FH (72V205) 003FH (72V215):

007FH (72V225/72V235/72V245)

FULL OFFSET REGISTER

17

11

0

DEFAULT VALUE

DEFAULT VALUE

001FH (72V205) 003FH (72V215):

007FH (72V225/72V235/72V245)

4294 drw 04

NOTE:

1. Any bits of the offset register not being programmed should be set to zero.

NOTE:

1. The same selection sequence applies to reading from the registers. REN is enabled and

read is performed on the LOW-to-HIGH transition of RCLK.