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72V811L10TFG Datasheet(PDF) 7 Page - Integrated Device Technology |
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72V811L10TFG Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 16 page 7 IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Figure 3. Offset Register Formats and Default Values for the A and B FIFOs containsfour8-bitoffsetregisterswhichcanbeloadedwithdataontheinputs, orreadontheoutputs. SeeFigure3fordetailsofthesizeoftheregistersand thedefaultvalues. IfFIFOA(B)isconfiguredtohaveprogrammableflags,whentheWENA1 (WENB1)andWENA2/LDA(WENB2/LDB)aresetLOW,dataontheDA(DB) inputsarewrittenintotheEmpty(LeastSignificantBit)Offsetregisteronthefirst LOW-to-HIGH transition of the WCLKA (WCLKB). Data are written into the Empty (Most Significant Bit) Offset register on the second LOW-to-HIGH transitionofWCLKA(WCLKB),intotheFull(LeastSignificantBit)Offsetregister onthethirdtransition,andintotheFull(MostSignificantBit)Offsetregisteron thefourthtransition. ThefifthtransitionofWCLKA(WCLKB)againwritestothe Empty(LeastSignificantBit)Offsetregister. 87 0 Empty Offset (LSB) Reg. Default Value 007H 80 Full Offset (LSB) Reg. Default Value 007H 7 80 Empty Offset (LSB) Default Value 007H 80 Full Offset (LSB) Default Value 007H 72V801 - 256 x 9 x 2 72V811 - 512 x 9 x 2 7 7 80 (MSB) 1 0 0 87 0 Empty Offset (LSB) Reg. Default Value 007H 80 Full Offset (LSB) Reg. Default Value 007H 7 80 Empty Offset (LSB) Default Value 007H 80 Full Offset (LSB) Default Value 007H 72V831 - 2,048 x 9 x 2 7 7 80 80 (MSB) 0000 2 (MSB) 000 3 80 80 (MSB) 0000 2 (MSB) 000 3 80 8 0 80 (MSB) 1 0 87 0 Empty Offset (LSB) Reg. Default Value 007H 80 Full Offset (LSB) Reg. Default Value 007H 7 72V821 - 1,024 x 9 x 2 80 (MSB) 00 1 80 (MSB) 00 1 4093 drw 05 72V841 - 4,096 x 9 x 2 80 Empty Offset (LSB) Default Value 007H 80 Full Offset (LSB) Default Value 007H 7 7 80 (MSB) 00000 4 72V851 - 8,192 x 9 x 2 (MSB) 00000 80 4 However,writingalloffsetregistersdoesnothavetooccuratonetime. One or two offset registers can be written and then by bringing LDA(LDB) HIGH, FIFOA(B)isreturnedtonormalread/writeoperation.WhenLDA(LDB)isset LOW, and WENA1 (WENB1) is LOW, the next offset register in sequence is written. ThecontentsoftheoffsetregisterscanbereadontheQA(QB)outputswhen WENA2/LDA (WENB2/LDB) is set LOW and both Read Enables RENA1, RENA2(RENB1,RENB2)aresetLOW. DatacanbereadontheLOW-to-HIGH transition of the Read Clock RCLKA (RCLKB). A read and write should not be performed simultaneously to the offset registers. |
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