CY7C409A-25VC datasheet(9/16 Pages) CYPRESS

Part #	CY7C409A-25VC

Description	64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY7C408A

CY7C409A

9

Possible Minimum Pulse Width Violation at the Boundary

Conditions

If the handshaking signals IR and OR are not properly used to

generate the SI and SO signals, it is possible to violate the

minimum (effective) SI and SO positive pulse widths at the full

and empty boundaries.

Cascading the 7C408/9A-35 Above 25 MHz

First, the capacity of N cascaded FIFOs is decreased from N

× 64 to (N × 63) + 1.

If cascaded FIFOs are to be operated with an external clock

rate greater than 25 MHz, the interface IR signal must be in-

verted before being fed back to the interface SO pin (

Figure

3). Two things should be noted when this configuration is im-

plemented.

Secondly, the frequency at the cascade interface is less than

the 35 MHz rate at which the external clocks may operate.

Therefore, the first device has its data shifted in faster than it

is shifted out, and eventually this device becomes momentarily

full. When this occurs, the maximum sustainable external

clock frequency changes from 35 MHz to the cascade inter-

face frequency.[28]

When data packets[29] are transmitted, this phenomenon does

not occur unless more than three FIFOs are depth cascaded.

For example, if two FIFOs are cascaded, a packet of 127 (=2

× 63 + 1) words may be shifted in at up to 35 MHz and then

the entire packet may be shifted out at up to 35 MHz.

Figure 2. Shifting Words Out.

C408A–18

SHIFT OUT

HF

AFE

64

63

FULL

56

55

54

30

9

8

7

32

31

1

EMPTY

Figure 3. Cascaded Configuration Above 25 MHz.

Figure 4. Cascaded Configuration at or below 25 MHz [22,23,24,25,26].

C408A–19

IR

SI

SO

OR

B

IR

SI

SO

OR

A

IR

SI

SO

OR

C

IR

SI

DIN

2

1

N

UPSTREAM

DOWNSTREAM

IRX

SIX

DINX

SOX

ORX

DOUTX

SO

OR

128 x 9 Configuration

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

OUTPUT READY

SHIFT IN

SHIFT OUT

INPUT READY

DATA IN

DATA OUT

MR

C408A–20

HF/AFE

DI4

DI5

DI6

DI7

DO4

DO5

DO6

DO7

DI4

DI5

DI6

DI7

DO4

DO5

DO6

DO7

DI8

DO8

DI8

DO8

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CY7C409A-25VC Datasheet(PDF) 9 Page - Cypress Semiconductor

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