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GLT5160L16I-7TC Datasheet(PDF) 11 Page - List of Unclassifed Manufacturers

Part # GLT5160L16I-7TC
Description  16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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GLT5160L16I-7TC Datasheet(HTML) 11 Page - List of Unclassifed Manufacturers

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11
G-LINK Technology
DEC. 2003 (Rev.2.4)
Read
After tRCD from the bank activation, a READ command can be
issued. 1st output data is available after the CAS Latency from the
READ, followed by (BL-1) consecutive data when the Burst Length
is BL. The start address is specified by A[7:0], and the address
sequence of burst data is defined by the Burst Type. A READ com-
mand may be applied to any active bank, so the row precharge time
(tRP) can be hidden behind continuous output data (in case of BL =
4) by interleaving the dual banks. When A[10] is high at a READ
command, the auto-precharge (READA) is performed. Any com-
mand (READ, WRITE, PRE, ACT) to the same bank is inhibited till
the internal precharge is complete. The internal precharge start tim-
ing depends on CAS Latency. The next ACT command can be
issued after tRP from the internal precharge timing.
CLK
Figure 4. Dual Bank Interleaving READ (BL=4, CL=3)
Command
A[9:0]
A[10]
BA
DQ
ACT
REA
ACT
PRE
Qa2
Qa1
Qa0
Qa3
REA
Xa
Ya
Xb
Yb
Xa
0
Xb
0
0
0
0
1
0
1
Qb0
Qb1
Qb2
tRCD
CAS Latency
Burst Length
CLK
Figure 5. READ with Auto-Precharge (BL=4, CL=3)
Command
A[9:0]
A[10]
BA
DQ
ACT
READ A
ACT
Qa2
Qa1
Qa0
Qa3
tRCD
Xa
Y
Xa
Xa
1
Xa
0
0
0
tRP
Internal Precharge begins
CLK
Figure 6. READ Auto-Precharge Timing (BL=4)
Command
CL=3 DQ
CL=2 DQ
ACT
READ A
Internal Precharge Start Timing
Qa2
Qa1
Qa0
Qa3
Qa2
Qa1
Qa0
Qa3


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