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GLT5160L16P-6FJ Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers |
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GLT5160L16P-6FJ Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers |
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2 / 45 page  2 G-LINK Technology DEC. 2003 (Rev. 2.4) FUNCTIONAL BLOCK DIAGRAM A[10:0] DQ[15:0] Figure 1. 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM Address Buffer BA CLK CKE CS RAS Clock Buffer Control Signal Buffer CAS WE DQML DQMU Mode Register Memory Array Bank #0 Memory Array Bank #1 I/O Buffer Signal Description Signal Type Description CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. CKE Input Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. CS Input Chip Select: When CS is high, any command means No Operation. RAS, CAS, WE Input Combination of RAS, CAS, WE defines basic commands. A[10:0] Input A[10:0] specify the Row / Column Address in conjunction with BA. The Row Address is specified by A[10:0]. The Column Address is specified by A[7:0]. A[10] is also used to indicate precharge option. When A[10] is high at a read / write command, an auto precharge is performed. When A[10] is high at a precharge command, both banks are precharged. BA Input Bank Address: BA is not simply A[11]. BA specifies the bank to which a command is applied. BA must be set with ACT, PRE, READ, WRITE commands. DQ[15:0] Input / Output Data In and Data out are referenced to the rising edge of CLK. DQML Input Lower Din[7:0] Mask / Lower Output[7:0] Disable: When DQML is high in burst write, lower Din[7:0] for the current cycle is masked. When DQML is high in burst read, lower Dout[7:0] is disabled at the next but one cycle. DQMU Input Upper Din[15:8] Mask / Upper Output[15:8] Disable: When DQMU is high in burst write, upper Din(8-15) for the current cycle is masked. When DQMU is high in burst read, upper Dout[15:8] is disabled at the next but one cycle. VDD, VSS Power Supply Power Supply for the memory array and peripheral circuitry. VDDQ, VSSQ Power Supply VDDQ and VSSQ are supplied to the Output Buffers only. |
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