4

SETTLING TIME TEST CIRCUIT

+

V-

0.001

µF

0.001

µF

1

µF

1

µF

2k

Ω

5k

Ω

V+

INPUT

500

Ω

SETTLING

POINT

200

Ω

OUTPUT

PROBE

MONITOR

-

NOTES:

13. Load Capacitance should be less than 10pF.

14. It is recommended that resistors be carbon composition

and that feedback and summing network ratios be

matched to 0.1%.

15. SETTLING POINT (Summing Node) capacitance should

be less than 10pF. For optimum settling time results, it is

recommended that the test circuit be constructed directly

onto the device pins. A Tektronix 568 Sampling

Oscilloscope with S-3A sampling heads is recommend-

ed as a settle point monitor.

FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS GAINS

FIGURE 2. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE

FIGURE 3. GAIN BANDWIDTH PRODUCT vs TEMPERATURE

FIGURE 4. CMRR vs FREQUENCY

100

80

60

40

20

0

0

90

180

1K

10K

100K

1M

10M

FREQUENCY (Hz)

OPEN LOOP

OPEN LOOP

100M

650

600

550

500

5

6

7

8

9

10

111213

14

15

SUPPLY VOLTAGE (

±V)

750

650

550

450

350

250

-60

-40

-20

0

20

40

60

80

100

120

140

100

10K

100K

1M

10M

FREQUENCY (Hz)

1K

90

80

70

60

50

40

30

20

HA-2840