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HD6433683 Datasheet(PDF) 9 Page - Renesas Technology Corp |
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HD6433683 Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 504 page Rev. 3.00, 05/03, page ix of xxx Contents Section 1 Overview........................................................................................... 1 1.1 Features ............................................................................................................................. 1 1.2 Internal Block Diagram..................................................................................................... 3 1.3 Pin Arrangement ............................................................................................................... 5 1.4 Pin Functions..................................................................................................................... 7 Section 2 CPU................................................................................................... 11 2.1 Address Space and Memory Map ..................................................................................... 12 2.2 Register Configuration ...................................................................................................... 15 2.2.1 General Registers ................................................................................................. 16 2.2.2 Program Counter (PC) ......................................................................................... 17 2.2.3 Condition-Code Register (CCR) .......................................................................... 17 2.3 Data Formats ..................................................................................................................... 19 2.3.1 General Register Data Formats ............................................................................ 19 2.3.2 Memory Data Formats ......................................................................................... 21 2.4 Instruction Set ................................................................................................................... 22 2.4.1 Table of Instructions Classified by Function ....................................................... 22 2.4.2 Basic Instruction Formats .................................................................................... 32 2.5 Addressing Modes and Effective Address Calculation ..................................................... 33 2.5.1 Addressing Modes ............................................................................................... 33 2.5.2 Effective Address Calculation.............................................................................. 36 2.6 Basic Bus Cycle ................................................................................................................ 38 2.6.1 Access to On-Chip Memory (RAM, ROM)......................................................... 38 2.6.2 On-Chip Peripheral Modules ............................................................................... 39 2.7 CPU States ........................................................................................................................ 40 2.8 Usage Notes ...................................................................................................................... 41 2.8.1 Notes on Data Access to Empty Areas................................................................. 41 2.8.2 EEPMOV Instruction........................................................................................... 41 2.8.3 Bit-Manipulation Instruction................................................................................ 41 Section 3 Exception Handling .......................................................................... 47 3.1 Exception Sources and Vector Address ............................................................................ 48 3.2 Register Descriptions ........................................................................................................49 3.2.1 Interrupt Edge Select Register 1 (IEGR1)............................................................ 50 3.2.2 Interrupt Edge Select Register 2 (IEGR2)............................................................ 51 3.2.3 Interrupt Enable Register 1 (IENR1) ................................................................... 52 3.2.4 Interrupt Enable Register 2 (IENR2) ................................................................... 53 3.2.5 Interrupt Flag Register 1 (IRR1) .......................................................................... 53 3.2.6 Interrupt Flag Register 2 (IRR2) .......................................................................... 55 |
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