Electronic Components Datasheet Search |
|
DS4510U-5 Datasheet(PDF) 9 Page - Maxim Integrated Products |
|
DS4510U-5 Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 12 page CPU Supervisor with Nonvolatile Memory and Programmable I/O _____________________________________________________________________ 9 time (see Figure 5) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device per- forms a NACK by transmitting a one during the 9th bit. Timing (Figure 5) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of informa- tion transferred from the master to the slave (most sig- nificant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the mas- ter are done according to the bit-write definition and the acknowledgement is read using the bit-read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition above, and the master transmits an ACK using the bit-write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return con- trol of SDA to the master. Slave Address and the R/ W Bit: Each slave on the I2C bus responds to a slave addressing byte sent immedi- ately following a start condition. The slave address byte contains the slave address and the R/ W bit. The slave address (see Figure 6) is the most significant 7 bits and the R/ W bit is the least significant bit. The DS4510’s slave address is 101000A0 (binary), where A0 is the value of the A0 address pin. The REGISTER LOCATION (HEX) REGISTER NAME FUNCTION 00 to 3F User EEPROM 64 bytes of EEPROM memory. 40 to EF Reserved These memory locations are reserved for future products. F0 Pullup Enable The four least significant bits of this register each enable/disable one of the internal pullup resistors. Set the bit to enable the pullup, clear it to disable the pullup. F1 RST Delay The two LSBs of this register (TD1 and TD0) select the reset delay (tRST) as shown in the CPU Supervisor AC Timing Characteristics. F2 to F3 User SEEPROM SRAM Shadowed EEPROM user byte. F4 to F7 I/OX Control Clearing the LSB of the register enables the I/OX pulldown transistor; setting the bit disables the pulldown transistor. F8 I/O Status This register reflects the logic level of the I/OX pins. The upper four bits of this register always read zero. F9 Config This register contains 5 bits that read and control the behavior of the part as follows: Bit Name Bit Function ready Reads zero when VCC is above the DS4510's power-on reset voltage. Trip Point Reads one when VCC below VCCTP. Reset Status Reads one when the RST pin is active. SEE When zero, writes to the SEEPROM registers behave like EEPROM. When one, writes to the SEEPROM registers behave like SRAM. SWRST Setting this bit activates the RST output. This bit automatically returns to zero during the RST active time. FA to FF User SRAM 6 bytes of SRAM memory Table 1. Register Definitions |
Similar Part No. - DS4510U-5 |
|
Similar Description - DS4510U-5 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |