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MLC852P Datasheet(PDF) 10 Page - Megawin Technology Co., Ltd |
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MLC852P Datasheet(HTML) 10 Page - Megawin Technology Co., Ltd |
10 / 35 page 10 MLC852P Technical Summary MEGAWIN TK12, TK11 and TK10: select timer 1 input clock source. TK12 TK11 TK10 Selected TM1 input clock source 0 0 0 FOSC 0 0 1 FOSC / 2 0 1 0 FOSC / 4 0 1 1 FOSC / 32 1 0 0 Fosc/128 1 0 1 P0.6 1 1 0 Un-used 1 1 1 Un-used Note that, if P0.6 is selected as the timer clock, user must configure the pin P0.6 as an input. I/O Ports Port 0 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 1208H P0 P07 P06 P05 P04 P03 P02 P01 P00 √ √ 1209H P0DIR DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 √ √ 120AH P0CONF CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0 √ √ 120BH P0PULL STR7 STR6 STR5 STR4 STR3 STR2 STR1 STR0 √ √ 120CH P0STB STB7 STB6 STB5 STB4 STB3 STB2 STB1 STB0 √ √ Port 0 is an 8-bit I/O port. Each pin can be programmed as input or output individually. P0 (Port 0 buffer) When Port0.n is configured as an output pin, the Port0.n pin would output the logic content of P0.n. Whether the Port0.n is configured as an input or an output pin, reading P0.n would always read the logic value from pad. P0DIR (Port 0 Direction) P0DIR.n = 0: P0.n is configured as an input pin. (Default) P0DIR.n = 1: P0.n is configured as an output pin. P0CONF (Port 0 pull-high/CMOS/NMOS setting) When P0DIR.n is 0 (input mode), P0CONF.n = 0: The weak internal pull-high resistor of P0.n is enabled. (Default) P0CONF.n = 1: The weak internal pull-high resistor of P0.n is disabled. When P0DIR.n is 1 (output mode), P0CONF.n = 0: P0.n is a CMOS output pin. (Default) P0CONF.n = 1: P0.n is a NMOS output pin. P0PULL (Port 0 pull-high resistor selection) P0PULL.n = 0: The strong pull-high resistor of P0.n is disabled. (Default) P0PULL.n = 1: The strong pull-high resistor of P0.n is enabled. |
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