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7019L15PFGI Datasheet(PDF) 1 Page - Integrated Device Technology |
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7019L15PFGI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 17 page  1 ©2013 Integrated Device Technology, Inc. SEPTEMBER 2013 DSC-4840/5 I/O Control Address Decoder 128Kx9 MEMORY ARRAY 7019 ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0L OEL R/ WL A16L A0L I/O0-8L SEML INTL (2) BUSYL (1,2) R/ WL CE0L OEL I/O Control Address Decoder OER R/ WR CE0R A16R A0R I/O0-8R SEMR INTR (2) R BUSY (1,2) M/ S (1) CE1L R/ WR CE0R OER CE1R 4840 drw 01 1L CE 1R CE 17 17 Functional Block Diagram than one device ◆ M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave ◆ Interrupt Flag ◆ On-chip port arbitration logic ◆ Full on-chip hardware support of semaphore signaling between ports ◆ Fully asynchronous operation from either port ◆ TTL-compatible, single 5V (±10%) power supply ◆ Available in a 100-pin TQFP ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Green parts available, see ordering information Features ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access – Commercial: 15/20ns (max.) – Industrial: 20ns (max.) ◆ Low-power operation – IDT7019L Active: 1W (typ.) Standby: 1mW (typ.) ◆ Dual chip enables allow for depth expansion without external logic ◆ IDT7019 easily expands data bus width to 18 bits or more using the Master/Slave select when cascading more HIGH-SPEED 128K x 9 DUAL-PORT STATIC RAM IDT7019L NOTES: 1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). |
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