Electronic Components Datasheet Search |
|
71421SA20PFGI Datasheet(PDF) 11 Page - Integrated Device Technology |
|
71421SA20PFGI Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 17 page 6.42 IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges 11 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) NOTES: 1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY." 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that a write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating (SA or LA).. 71321X20 71421X20 Com'l Only 71321X25 71421X25 Com'l & Ind Symbol Parameter Min.Max.Min.Max. Unit BUSY TIMING (For MASTER 71321) tBAA BUSY Access Time from Address ____ 20 ____ 20 ns tBDA BUSY Disable Time from Address ____ 20 ____ 20 ns tBAC BUSY Access Time from Chip Enable ____ 20 ____ 20 ns tBDC BUSY Disable Time from Chip Enable ____ 20 ____ 20 ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ ns tWDD Write Pulse to Data Delay(1) ____ 50 ____ 50 ns tDDD Write Data Valid to Read Data Delay (1) ____ 35 ____ 35 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data(3) ____ 25 ____ 35 ns BUSY INPUT TIMING (For SLAVE 71421) tWB Write to BUSY Input(4) 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ ns tWDD Write Pulse to Data Delay(1) ____ 40 ____ 50 ns tDDD Write Data Valid to Read Data Delay (1) ____ 30 ____ 35 ns 2691 tbl 10a 71321X35 71421X35 Com'l Only 71321X55 71421X55 Com'l & Ind Symbol Parameter Min.Max.Min.Max. Unit BUSY TIMING (For MASTER 71321) tBAA BUSY Access Time from Address ____ 20 ____ 30 ns tBDA BUSY Disable Time from Address ____ 20 ____ 30 ns tBAC BUSY Access Time from Chip Enable ____ 20 ____ 30 ns tBDC BUSY Disable Time from Chip Enable ____ 20 ____ 30 ns tWH Write Hold After BUSY(5) 20 ____ 20 ____ ns tWDD Write Pulse to Data Delay(1) ____ 60 ____ 80 ns tDDD Write Data Valid to Read Data Delay(1) ____ 35 ____ 55 ns tAPS Arbitration Priority Set-up Time(2) 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data(3) ____ 35 ____ 50 ns BUSY INPUT TIMING (For SLAVE 71421) tWB Write to BUSY Input(4) 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 20 ____ 20 ____ ns tWDD Write Pulse to Data Delay(1) ____ 60 ____ 80 ns tDDD Write Data Valid to Read Data Delay(1) ____ 35 ____ 55 ns 2691 tbl 10b |
Similar Part No. - 71421SA20PFGI |
|
Similar Description - 71421SA20PFGI |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |