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70121L55JGI8 Datasheet(PDF) 6 Page - Integrated Device Technology |
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70121L55JGI8 Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 16 page  6.42 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges 6 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter guaranteed by device characterization, but is not production tested. 3. 'X' in part numbers indicates power rating (S or L). 70121X25 70125X25 Com'l Only 70121X35 70125X35 Com'l & Ind Unit Symbol Parameter Min. Max. Min. Max. READ CYCLE tRC Read Cycle Time 25 ____ 35 ____ ns tAA Address Access Time ____ 25 ____ 35 ns tACE Chip Enable Access Time ____ 25 ____ 35 ns tAOE Output Enable Access Time ____ 12 ____ 25 ns tOH Output Hold from Address Change 0 ____ 0 ____ ns tLZ Output Low-Z Time(1,2) 0 ____ 0 ____ ns tHZ Output High-Z Time(1,2) ____ 10 ____ 15 ns tPU Chip Enable to Power Up Time(2) 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time(2) ____ 50 ____ 50 ns 2654 tbl 09a 70121X55 70125X55 Com'l Only Unit Symbol Parameter Min. Max. READ CYCLE tRC Read Cycle Time 55 ____ ns tAA Address Access Time ____ 55 ns tACE Chip Enable Access Time ____ 55 ns tAOE Output Enable Access Time ____ 35 ns tOH Output Hold from Address Change 0 ____ ns tLZ Output Low-Z Time(1,2) 0 ____ ns tHZ Output High-Z Time(1,2) ____ 30 ns tPU Chip Enable to Power Up Time(2) 0 ____ ns tPD Chip Disable to Power Down Time(2) ____ 50 ns 2654 tbl 09b |
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