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72265LA10TFGI8 Datasheet(PDF) 2 Page - Integrated Device Technology |
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72265LA10TFGI8 Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 27 page 2 IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATIONS TQFP (PN64, ORDER CODE: PF) STQFP (PP64, ORDER CODE: TF) TOP VIEW DESCRIPTION (CONTINUED) PIN 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 WEN SEN DC VCC GND D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Q17 Q16 GND Q15 Q14 VCC Q13 Q12 Q11 GND Q10 Q9 Q8 Q7 Q6 GND 4670 drw02 SuperSync FIFOs are particularly appropriate for networking, video, telecommunications,datacommunicationsandotherapplicationsthatneedto bufferlargeamountsofdata. TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable (WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen WEN is asserted. The output port is controlled by a Read Clock (RCLK) input andReadEnable(REN)input. DataisreadfromtheFIFOoneveryrisingedge of RCLK when REN is asserted. An Output Enable (OE) input is provided for three-statecontroloftheoutputs. The frequencies of both the RCLK and the WCLK signals may vary from 0 tofMAXwithcompleteindependence.Therearenorestrictionsonthefrequency of one clock input with respect to the other. Therearetwopossibletimingmodesofoperationwiththesedevices:IDT Standard mode and First Word Fall Through (FWFT) mode. InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread operation,whichconsistsofactivatingRENandenablingarisingRCLKedge, willshiftthewordfrominternalmemorytothedataoutputlines. NOTE: 1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open. |
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