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7052S25PFG8 Datasheet(PDF) 7 Page - Integrated Device Technology |
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7052S25PFG8 Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 12 page  6.42 IDT7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges 7 2674 drw 08 tAOE tLZ tHZ DATAOUT CE tACE VALID DATA OE CURRENT ICC ISB tPU 50% tLZ tPD 50% tHZ 2674 drw 07 tAA tOH tOH DATAOUT ADDRESS tRC DATA VALID PREVIOUS DATA VALID Timing Waveform of Read Cycle No. 1, Any Port(1) AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(3) NOTES: 1. Transition is measured 0mV from Low or High-Impedance voltage with the Output Test Load (Figure 2) 2. This parameter is guaranteed by device characterization but is not production tested. 3. 'X' in part number indicates power rating (S or L) Timing Waveform of Read Cycle No. 2, Any Port(1,2) NOTE: 1. R/W = VIH, OE = VIL and CE = VIL. NOTES: 1. R/W = VIH for Read Cycles. 2. Addresses valid prior to or coincident with CE transition LOW. 7052X20 Com'l Only 7052X25 Com'l, Ind & Military 7052X35 Com'l & Military Symbol Parameter Min. Max.Min.Max.Min. Max. Unit READ CYCLE tRC Read Cycle Time 20 ____ 25 ____ 35 ____ ns tAA Address Access Time ____ 20 ____ 25 ____ 35 ns tACE Chip Enable Access Time ____ 20 ____ 25 ____ 35 ns tAOE Output Enable Access Time ____ 10 ____ 15 ____ 25 ns tOH Output Hold from Address Change 0 ____ 0 ____ 0 ____ ns tLZ Output Low-Z Time(1,2) 5 ____ 5 ____ 5 ____ ns tHZ Output High-Z Time(1,2) ____ 12 ____ 15 .____ 15 ns tPU Chip Enable to Power Up Time(2) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time(2) ____ 20 ____ 25 ____ 35 ns 2674 tbl 09 |
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