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70261S25PFG Datasheet(PDF) 1 Page - Integrated Device Technology |
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70261S25PFG Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 20 page  ©2015 Integrated Device Technology, Inc. JUNE 2015 DSC 3039/11 1 HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial 20/25ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT70261S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT70261L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ ◆ ◆ ◆ ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ ◆ ◆ ◆ ◆ IDT70261 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave ◆ ◆ ◆ ◆ ◆ Busy and Interrupt Flags ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ ◆ ◆ ◆ ◆ TTL-compatible, single 5V (±10%) power supply ◆ ◆ ◆ ◆ ◆ Available in 100-pin Thin Quad Flatpack ◆ ◆ ◆ ◆ ◆ Industrial temperature range (-40OC to +85OC) is available for selected speeds ◆ ◆ ◆ ◆ ◆ Green parts available. See ordering information Functional Block Diagram NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull. IDT70261S/L I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/WL BUSYL A13L A0L 3039 drw 01 UBL LBL CEL OEL I/O8L-I/O15L I/O0L-I/O7L CEL OEL R/ WL SEML INTL M/ S R/WR BUSYR UBR LBR CER OER I/O8R-I/O15R I/O0R-I/O7R A13R A0R R/ WR SEMR INTR CER OER (2) (1,2) (1,2) (2) 14 14 |
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