COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

8

©

NOTE:

Figure 5. Write Cycle Timing

NOTES:

1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable

flag offset registers.

2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.

3. The clocks (RCLK, WCLK) can be free-running during reset.

Figure 4. Reset Timing

RS

REN1, REN2

OE = 1

OE = 0

(2)

EF, PAE

FF, PAF

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WEN1

(1)

WEN2/

LD

(1)

WCLK

WEN1

WEN2/

(If Applicable)

FF

RCLK

REN1,

REN2

NO OPERATION

NO OPERATION

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DATA IN VALID