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7052L35PFGB Datasheet(PDF) 9 Page - Integrated Device Technology |
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7052L35PFGB Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 12 page 6.42 IDT7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges 9 Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(5,8) Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1, 5) NOTES: 1. R/W or CE = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL. 3. tWR is measured from the earlier of CE or R/W = VIH to the end of write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed but is not production tested. 8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. CE 2674 drw 09 tAW tAS tWR tDW DATAIN ADDRESS tWC R/ W tWP DATAOUT tWZ (7) (4) (4) (2) tOW OE tHZ tLZ (7) tHZ (6) (3) (9) tDH (7) CE 2674 drw 10 tAW tAS tWR tDW DATAIN ADDRESS tWC R/ W tEW tDH (9) (6) (2) (3) |
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