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72215LB15TFGI8 Datasheet(PDF) 8 Page - Integrated Device Technology

Part # 72215LB15TFGI8
Description  CMOS SyncFIFO
Download  16 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

72215LB15TFGI8 Datasheet(HTML) 8 Page - Integrated Device Technology

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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
MARCH 2013
Afterhalfofthememoryisfilled,andattheLOW-to-HIGHtransitionofthenext
writecycle,theHalf-FullFlaggoesLOWandwillremainsetuntilthedifference
between the write pointer and read pointer is less than or equal to one half of
the total memory of the device. The Half-Full Flag (HF) is then reset to HIGH
by the LOW-to-HIGH transition of the Read Clock (RCLK). The HF is
asynchronous.
In the Daisy Chain Depth Expansion mode, WXI is connected to WXO of
thepreviousdevice. ThisoutputactsasasignaltothenextdeviceintheDaisy
Chainbyprovidingapulsewhenthepreviousdevicewritestothelastlocation
ofmemory.
READ EXPANSION OUT (RXO)
In the Daisy Chain Depth Expansion configuration, Read Expansion In
(RXI)isconnectedtoReadExpansionOut(RXO)ofthepreviousdevice.This
outputactsasasignaltothenextdeviceintheDaisyChainbyprovidingapulse
when the previous device reads from the last location of memory.
DATAOUTPUTS(Q0-Q17)
Q0-Q17 are data outputs for 18-bit wide data.
,
,
,
,
,
t
t
t
t
RSF
RSF
RS
RSR
Q0 - Q17
t RSF
= 0
= 1
(1)
2766 drw 06
tRSS
NOTES:
1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
2. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing(2)


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