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72255LA15TFG Datasheet(PDF) 3 Page - Integrated Device Technology |
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72255LA15TFG Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 27 page  3 IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES DESCRIPTION (CONTINUED) Figure 1. Block Diagram of Single 8,192 x 18 and 16,384 x 18 Synchronous FIFO DATA OUT (Q0 - Qn) DATA IN (D0 - Dn) MASTER RESET ( MRS) READ CLOCK (RCLK) READ ENABLE ( REN) OUTPUT ENABLE ( OE) EMPTY FLAG/OUTPUT READY ( EF/OR) PROGRAMMABLE ALMOST-EMPTY ( PAE) WRITE CLOCK (WCLK) WRITE ENABLE ( WEN) LOAD ( LD) FULL FLAG/INPUT READY ( FF/IR) PROGRAMMABLE ALMOST-FULL ( PAF) IDT 72255LA 72265LA PARTIAL RESET ( PRS) FIRST WORD FALL THROUGH/SERIAL INPUT (FWFT/SI) RETRANSMIT ( RT) 4670 drw03 HALF FULL FLAG ( HF) SERIAL ENABLE( SEN) InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectlyto thedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoesnot havetobeassertedforaccessingthefirstword.However,subsequentwords writtentotheFIFOdorequireaLOWonRENforaccess. ThestateoftheFWFT/ SIinputduringMasterResetdeterminesthetimingmodeinuse. ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFOcan provide, the FWFT timing mode permits depth expansion by chaining FIFOs inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding data inputs of the next). No external logic is required. TheseFIFOshavefiveflagpins,EF/OR(EmptyFlagorOutputReady),FF/ IR(FullFlagorInputReady),HF(Half-fullFlag),PAE(ProgrammableAlmost- Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFFfunctions are selected in IDT Standard mode. The IRandORfunctionsareselectedin FWFT mode. HF, PAE and PAF are always available for use, irrespective of timingmode. PAE and PAF can be programmed independently to switch at any point in memory. (SeeTableIandTable2.) Programmableoffsetsdeterminetheflag switchingthresholdandcanbeloadedbytwomethods:parallelorserial. Two defaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchat127 or1,023locationsfromtheemptyboundaryandthePAFthresholdcanbeset at127or1,023locationsfromthefullboundary. Thesechoicesaremadewith the LD pin during Master Reset. For serialprogramming,SENtogetherwithLDoneachrisingedgeofWCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused to load the offset registers via Dn. REN together with LD on each rising edge ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether serialorparalleloffsetloadinghasbeenselected. DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite pointers are set to the first location of the FIFO. The FWFT pin selects IDT StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023 withserialprogramming. Theflagsareupdatedaccordingtothetimingmode anddefaultoffsetsselected. The Partial Reset (PRS) also sets the read and write pointers to the first locationofthememory. However,thetimingmode,partialflagprogramming method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset remainunchanged.Theflagsareupdatedaccordingtothetimingmodeand offsets in effect. PRS is useful for resetting a device in mid-operation, when reprogrammingpartialflagswouldbeundesirable. TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit operationbysettingthereadpointertothefirstlocationofthememoryarray. If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol inputs)willimmediatelytakethedeviceoutofthepowerdownstate. The IDT72255LA/72265LA are fabricated using IDT’s high speed submi- cronCMOStechnology. |
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