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72815LB10BGG Datasheet(PDF) 1 Page - Integrated Device Technology |
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72815LB10BGG Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 26 page  1 MAY 2016 CMOS DUAL SyncFIFO™ DUAL 256 x 18 DUAL 512 x 18 DUAL 1,024 x 18 DUAL 4,096 x 18 IDT72805LB IDT72815LB IDT72825LB IDT72845LB COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc. ©2016IntegratedDeviceTechnology,Inc.Allrightsreserved.Productspecificationssubjecttochangewithoutnotice. DSC-3139/9 FEATURES: ••••• The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs ••••• The IDT72815LB is equivalent to two IDT72215LB 512 x 18 FIFOs ••••• The IDT72825LB is equivalent to two IDT72225LB 1,024 x 18 FIFOs ••••• The IDT72845LB is equivalent to two IDT72245LB 4,096 x 18 FIFOs ••••• Offers optimal combination of large capacity (8K), high speed, design flexibility, and small footprint ••••• Ideal for the following applications: - Network switching - Two level prioritization of parallel data - Bidirectional data transfer - Bus-matching between 18-bit and 36-bit data paths - Width expansion to 36-bit per package - Depth expansion to 8,192 words per package ••••• 10ns read/write cycle time, 6.5ns access time ••••• IDT Standard or First Word Fall Through timing ••••• Single or double register-buffered Empty and Full Flags FUNCTIONAL BLOCK DIAGRAM ••••• Easily expandable in depth and width ••••• Asynchronous or coincident Read and Write clocks ••••• Asynchronous or synchronous programmable Almost-Empty and Almost-Full flags with default settings ••••• Half-Full flag capability ••••• Output Enable puts output data bus in high-impedance state ••••• High-performance submicron CMOS technology ••••• Available in the 128-pin Thin Quad Flatpack (TQFP). Also available for the IDT72805LB/72815LB/72825LB, in the 121-lead, 16 x 16 mm plastic Ball Grid Array (PBGA) ••••• Industrial temperature range (–40 °°°°°C to +85°°°°°C) is available ••••• Green parts available, see ordering information DESCRIPTION: The IDT72805LB/72815LB/72825LB/72845LB are dual 18-bit-wide syn- chronous (clocked) First-in, First-out (FIFO) memories. One dual IDT72805LB/ INPUT REGISTER OUTPUT REGISTER OFFSET REGISTER FLAG LOGIC FFA/IR A PAFA EF A/ ORA PAEA HF A/(WXOA) READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER EXPANSION LOGIC RESET LOGIC WENA DA0-DA17 LDA RSA ( HF A)/WXOA WXIA RENA RCLKA OEA QA0-QA17 RXOA RXIA FL A WCLKA INPUT REGISTER OUTPUT REGISTER RAM ARRAY 256 x 18 512 x 18 1,024 x 18 4,096 x 18 OFFSET REGISTER FLAG LOGIC FFB/IRB PAF B EF B/ORB PAEB HF B/(WXOB) READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER EXPANSION LOGIC RESET LOGIC WENB DB0-DB17 LDB RSB ( HF B)/WXOB WXIB RENB RCLKB OEB QB0-QB17 RXOB RXIB FL B WCLKB 3139 drw 01 RAM ARRAY 256 x 18 512 x 18 1,024 x 18 4,096 x 18 |
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