9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18

NOTES:

1. In a daisy-chain depth expansion, FL is held LOW for the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.

2. In a daisy-chain depth expansion, FL is held HIGH for members of the expansion other than the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and

WXO outputs of the preceding device.

TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET

FL

RXI

WXI

EF/OR

FF/IR

PAE, PAF

FIFO TIMING MODE

0

0

0

Single register-buffered

Single register-buffered

Asynchronous

Standard

Empty Flag

Full Flag

0

0

1

Triple register-buffered

Double register-buffered

Asynchronous

FWFT

Output Ready Flag

Input Ready Flag

0

1

0

Double register-buffered

Double register-buffered

Asynchronous

Standard

Empty Flag

Full Flag

1

1

Single register-buffered

Single register-buffered

Asynchronous

Standard

Empty Flag

Full Flag

1

0

0

Single register-buffered

Single register-buffered

Synchronous

Standard

Empty Flag

Full Flag

1

0

1

Triple register-buffered

Double register-buffered

Synchronous

FWFT

Output Ready Flag

Input Ready Flag

1

1

0

Double register-buffered

Double register-buffered

Synchronous

Standard

Empty Flag

Full Flag

1

1

Single register-buffered

Single register-buffered

Asynchronous

Standard

Empty Flag

Full Flag

TABLE 4 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — IDT STANDARD MODE

Empty Flag (EF)

Full Flag (FF)

Partial Flags

Programming at Reset

Flag Timing

Buffered Output

Buffered Output

Timing Mode

FL

RXI

WXI

Diagrams

Single

Single

Asynch

0

0

0

Figure 9, 10

Single

Single

Sync

1

0

0

Figure 9, 10

Double

Double

Asynch

0

1

0

Figure 24, 26

Double

Double

Synch

1

1

0

Figure 24, 26

TABLE 5 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — FWFT MODE

Output Ready (OR)

Input Ready (IR)

Partial Flags

Programming at Reset

Flag Timing

FL

RXI

WXI

Diagrams

Triple

Double

Asynch

0

0

1

Figure 27

Triple

Double

Sync

1

0

1

Figure 20, 21