1

©

AUGUST 2013

64 x 9, 256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9 and 8,192 x 9

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT72421,IDT72201

IDT72211,IDT72221

IDT72231,IDT72241

IDT72251

2013

Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

DSC-2655/6

FEATURES:

to any depth

Empty+7, and Full-7, respectively

32-pin Thin Quad Flat Pack (TQFP)

72220/72230/72240 data sheet

°°°°°C to +85°°°°°C) is available

FUNCTIONAL BLOCK DIAGRAM

WCLK

WEN1

WEN2

LD

OFFSET REGISTER

INPUT REGISTER

RAM ARRAY

64 x 9, 256 x 9,

512 x 9, 1,024 x 9,

2,048 x 9, 4,096 x 9,

8,192 x 9

WRITE CONTROL

LOGIC

WRITE POINTER

OUTPUT REGISTER

READ CONTROL

LOGIC

READ POINTER

FLAG

LOGIC

EF

PAE

PAF

FF

RESET LOGIC

OE

REN2

REN1

RS

RCLK

2655 drw01

DESCRIPTION:

The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™

are very high-speed, low-power First-In, First-Out (FIFO) memories with

clocked read and write controls. These devices have a 64, 256, 512, 1,024,

2,048,4,096,and8,192x9-bitmemoryarray,respectively. TheseFIFOsare

applicableforawidevarietyofdatabufferingneedssuchasgraphics,localarea

networksandinterprocessorcommunication.

TheseFIFOshave9-bitinputandoutputports.Theinputportiscontrolled

by a free-running clock (WCLK), and two write enable pins (WEN1, WEN2).

Data is written into the Synchronous FIFO on every rising clock edge when

thewriteenablepinsareasserted.Theoutputportiscontrolledbyanotherclock

pin (RCLK) and two read enable pins (REN1, REN2). The Read Clock can

be tied to the Write Clock for single clock operation or the two clocks can run

asynchronous of one another for dual-clock operation. An output enable pin

(OE) is provided on the read port for three-state control of the output.

The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).

Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are

provided for improved system control. The programmable flags default to

Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag

offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting

the load pin (LD).

TheseFIFOsarefabricatedusinghigh-speedsubmicronCMOStechnology.