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71321SA35JG Datasheet(PDF) 10 Page - Integrated Device Technology |
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71321SA35JG Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 17 page 6.42 IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges 10 Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5) Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8) NOTES: 1. R/ W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL. 3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the l/O pins are in the output state and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal ( CE or R/W) is asserted last. 7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. ADDRESS OE CE R/ W DATA OUT DATA IN (4) (4) 2691 drw 08 tWC tAS (6) tWR (3) tOW tDW tDH tAW tWP (2) tHZ (7) tWZ (7) tHZ (7) tWC ADDRESS CE R/ W DATAIN tAS (6) tEW (2) tWR tDW tDH tAW 2691 drw 09 (3) |
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