10

IDT7132SA/LA and IDT 7142SA/LA

High Speed 2K x 8 Dual Port Static RAM

Military, Industrial and Commercial Temperature Ranges

ADDRESS

CE

R/

W

(6)

(2)

(3)

2692 drw 10

NOTES:

1. R/W or CE must be HIGH during all address transitions.

4. During this period, the l/O pins are in the output state and input signals must not be applied.

5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

ADDRESS

OE

CE

R/

W

(6)

(2)

(7)

(4)

(4)

(7)

(7)

2692 drw 09

(3)