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72841L25TFGI Datasheet(PDF) 7 Page - Integrated Device Technology |
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72841L25TFGI Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 10 page 7 IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURERANGES MARCH 2013 LDA LDA LDA LDA LDA WENA1 WENA1 WENA1 WENA1 WENA1 WCLKA OPERATION ON FIFO A LDB LDB LDB LDB LDB WENB1 WENB1 WENB1 WENB1 WENB1 WCLKB OPERATION ON FIFO B 00 Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) 0 1 NoOperation 1 0 Write Into FIFO 1 1 NoOperation Figure 3. Offset Register Formats and Default Values for the A and B FIFOs Figure 2. Writing to Offset Registers for FIFOs A and B A read and write should not be performed simultaneously to the offset registers. OUTPUTS: Full Flag (FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write operations,when ArrayA(B)isfull. Ifnoreadsareperformedafterreset,FFA (FFB) will go LOW after 256 writes to the IDT72801's FIFO A (B); 512 writes totheIDT72811'sFIFOA(B);1,024writestotheIDT72821'sFIFOA(B);2,048 writes to the IDT72831's FIFO A (B); 4,096 writes to the IDT72841's FIFO A (B); or 8,192 writes to the IDT72851's FIFO A (B). FFA(FFB)issynchronizedwithrespecttotheLOW-to-HIGHtransitionofthe WriteClockWCLKA(WCLKB). EmptyFlag(EFA, EFB)—EFA(EFB)willgoLOW,inhibitingfurtherread operations,whenthereadpointerisequaltothewritepointer,indicatingthat Array A (B) is empty. EFA(EFB)is synchronizedwithrespecttotheLOW-to-HIGHtransitionof the Read Clock RCLKA (RCLKB). 87 0 Empty Offset (LSB) Reg. Default Value 007H 80 Full Offset (LSB) Reg. Default Value 007H 7 80 Empty Offset (LSB) Default Value 007H 80 Full Offset (LSB) Default Value 007H 72801 - DUAL 256 x 9 72811 - DUAL 512 x 9 7 7 80 (MSB) 1 00 87 0 Empty Offset (LSB) Reg. Default Value 007H 80 Full Offset (LSB) Reg. Default Value 007H 7 80 Empty Offset (LSB) Default Value 007H 80 Full Offset (LSB) Default Value 007H 72831 - DUAL 2,048 x 9 72851 - DUAL 8,192 x 9 7 7 80 80 (MSB) 0 2 (MSB) 0 3 80 80 (MSB) 0 2 (MSB) 0 3 80 8 0 80 (MSB) 1 0 3034 drw 04 80 Empty Offset (LSB) Default Value 007H 80 Full Offset (LSB) Default Value 007H 72841 - DUAL 4,096 x 9 7 7 80 (MSB) 0 4 80 (MSB) 0 4 80 Empty Offset (LSB) Default Value 007H 80 Full Offset (LSB) Reg. Default Value 007H 72821 - DUAL 1,024 x 9 7 7 80 (MSB) 0 1 80 (MSB) 0 1 NOTE: 1. For the purposes of this table, WENA2 and WENB2 = VIH. 2. The same selection sequence applies to reading from the registers. RENA1 and RENA2 (RENB1 and RENB2) are enabled and read is performed on the LOW-to- HIGH transition of RCLKA (RCLKB). |
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