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7016S25JGB Datasheet(PDF) 8 Page - Integrated Device Technology |
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7016S25JGB Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 21 page 6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges 8 tRC R/ W CE ADDR tAA OE 3190 drw 07 (4) tACE (4) tAOE (4) (1) tLZ tOH (2) tHZ (3,4) tBDD DATAOUT BUSYOUT VALID DATA (4) Waveform of Read Cycles(5) NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, CE or OE. 3. tBDDdelay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation tovalidoutputdata. 4. Startofvaliddatadependsonwhichtimingbecomeseffectivelast:tAOE,tACE,tAAortBDD. 5. SEM = VIH. Timing of Power-Up / Power-Down CE 3190 drw 08 tPU ICC ISB tPD 50% 50% , |
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