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72235LB25PFGI Datasheet(PDF) 3 Page - Integrated Device Technology |
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72235LB25PFGI Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 16 page 3 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES MARCH 2013 PIN DESCRIPTION Symbol Name I/O Description D0–D17 DataInputs I Data inputs for a 18-bit bus. RS Reset I WhenRS issetLOW,internalreadandwritepointersaresettothefirstlocationoftheRAMarray,FFand PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up. WCLK WriteClock I WhenWENisLOW,dataiswrittenintotheFIFOonaLOW-to-HIGHtransitionofWCLK,iftheFIFOisnotfull. WEN WriteEnable I When WEN is LOW and LD is HIGH, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF isLOW. RCLK Read Clock I WhenRENisLOW,dataisreadfromtheFIFOonaLOW-to-HIGHtransitionofRCLK,iftheFIFOisnotempty. REN Read Enable I When REN is LOW, and LD is HIGH, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the EF isLOW. OE OutputEnable I WhenOEisLOW,thedataoutputbusisactive.IfOE isHIGH,theoutputdatabuswillbeinahigh-impedance state. LD Load I When LDisLOW,dataontheinputsD0–D11iswrittentotheoffsetanddepthregistersontheLOW-to-HIGH transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the offset and depth registers on the LOW-to-HIGH transition of the RCLK, when REN is LOW. FL FirstLoad I Inthesingledeviceorwidthexpansionconfiguration,FLisgrounded.Inthedepthexpansionconfiguration,FL is grounded on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain. WXI WriteExpansion I Inthesingledeviceorwidthexpansionconfiguration,WXI isgrounded.Inthedepthexpansionconfiguration, WXI is connected to WXO (Write Expansion Out) of the previous device. RXI Read Expansion I Inthesingledeviceorwidthexpansionconfiguration, RXI isgrounded.Inthedepthexpansionconfiguration, RXI is connected to RXO (Read Expansion Out) of the previous device. FF Full Flag O WhenFFisLOW,theFIFOisfullandfurtherdatawritesintotheinputareinhibited.WhenFFisHIGH,theFIFO is not full. FF is synchronized to WCLK. EF EmptyFlag O WhenEFisLOW,theFIFOisemptyandfurtherdatareadsfromtheoutputareinhibited.WhenEFisHIGH,the FIFO is not empty. EF is synchronized to RCLK. PAE Programmable O When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO. The default Almost-EmptyFlag offset at reset is 31 from empty for IDT72205LB, 63 from empty for IDT72215LB, and 127 from empty for IDT72225LB/72235LB/72245LB. PAF Programmable O WhenPAFisLOW,theFIFOisalmost-fullbasedontheoffsetprogrammedintotheFIFO.Thedefaultoffsetat Almost-FullFlag reset is 31 from full for IDT72205, 63 from full for IDT72215LB, and 127 from full for IDT72225LB/72235LB/ 72245LB. WXO/HF WriteExpansion O In the single device or width expansion configuration, the device is more than half full when HF is LOW. In the Out/Half-FullFlag depthexpansionconfiguration,apulseissentfromWXOtoWXIofthenextdevicewhenthelastlocationinthe FIFOiswritten. RXO Read Expansion O In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last Out location in the FIFO is read. Q0–Q17 DataOutputs O Data outputs for an 18-bit bus. VCC Power +5V power supply pins. GND Ground Eight ground pins for the PLCC and seven gound pins for the TQFP/STQFP. |
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