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MARCH 2013

IDT72205LB, IDT72215LB,

IDT72225LB, IDT72235LB,

IDT72245LB

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

DSC-2766/3

256 x 18, 512 x 18, 1,024 x 18,

2,048 x 18, and 4,096 x 18

FEATURES:

default settings

and plastic leaded chip carrier (PLCC)

°°°°°C to +85°°°°°C) is available

DESCRIPTION:

The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high

speed,low-powerFirst-In,First-Out(FIFO)memorieswithclockedreadand

FUNCTIONAL BLOCK DIAGRAM

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY

256 x 18, 512 x 18

1,024 x 18, 2,048 x 18

4,096 x 18

•

•

••

OFFSET REGISTER

FLAG

LOGIC

/(

)

READ POINTER

READ CONTROL

LOGIC

WRITE CONTROL

LOGIC

WRITE POINTER

EXPANSION LOGIC

RESET LOGIC

WCLK

D0-D17

(

)/

RCLK

Q0-Q17

2766 drw 01

writecontrols.TheseFIFOsareapplicableforawidevarietyofdatabuffering

needs, such as optical disk controllers, Local Area Networks (LANs), and

interprocessorcommunication.

TheseFIFOshave18-bitinputandoutputports.Theinputportiscontrolled

byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataisread

intothesynchronousFIFOoneveryclockwhenWENisasserted.Theoutput

portiscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).

The read clock can be tied to the write clock for single clock operation or the

twoclockscanrunasynchronousofoneanotherfordual-clockoperation. An

Output Enable pin (OE) is provided on the read port for three-state control of

theoutput.

The synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF),

andtwoprogrammableflags,Almost-Empty(PAE)andAlmost-Full(PAF).The

offsetloadingoftheprogrammableflagsiscontrolledbyasimplestatemachine,

andisinitiatedbyassertingtheLoadpin(LD). AHalf-Fullflag(HF)isavailable

when the FIFO is used in a single device configuration.

ThesedevicesaredepthexpandableusingaDaisy-Chaintechnique.The

XI and XO pins are used to expand the FIFOs. In depth expansion configu-

ration, First Load (FL) is grounded on the first device and set to HIGH for all

other devices in the Daisy Chain.

The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated

using high-speed submicron CMOS technology.