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72245LB10JG8 Datasheet(PDF) 9 Page - Integrated Device Technology |
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72245LB10JG8 Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 16 page 9 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES MARCH 2013 NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. Figure 5. Write Cycle Timing Figure 6. Read Cycle Timing WCLK D0 - D17 t CLK t CLKH t CLKL t DS tENS t DH tENH tWFF t WFF DATA IN VALID NO OPERATION RCLK SKEW1 t (1) 2766 drw 07 NOTE: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge. NO OPERATION RCLK t CLK t CLKH t CLKL t ENS tENH tREF t REF VALID DATA tA t OLZ t OE t OHZ Q0 - Q17 WCLK SKEW2 t (1) 2766 drw 08 |
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