Specifications ispLSI 1048E

8

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

Table 2-0036B/1048E

Inputs

UNITS

-70

MIN.

-50

MIN.

MAX.

MAX.

DESCRIPTION

#

2

PARAMETER

22 I/O Register Bypass

–

–

0.7

ns

23 I/O Latch Delay

–

–

4.7

ns

29 GRP Delay, 1 GLB Load

–

–

5.1

ns

GLB

36 1 Product Term/XOR Path Delay

–

–

10.5

ns

37 20 Product Term/XOR Path Delay

–

–

10.5

ns

38 XOR Adjacent Path Delay

–

–

11.7

ns

39 GLB Register Bypass Delay

–

–

2.2

ns

40 GLB Register Setup Time before Clock

–

0.0

–

ns

41 GLB Register Hold Time after Clock

–

11.5

–

ns

42 GLB Register Clock to Output Delay

–

–

3.0

ns

3

43 GLB Register Reset to Output Delay

–

–

7.3

ns

44 GLB Product Term Reset to Register Delay

–

–

7.9

ns

45 GLB Product Term Output Enable to I/O Cell Delay

–

–

10.0

ns

46 GLB Product Term Clock Delay

6.9

8.3

ns

ORP

0.6

3.6

GRP

3.5

34 4 Product Term Bypass Path Delay (Combinatorial)

–

–

10.7

ns

8.4

8.4

9.4

1.6

8.5

35 4 Product Term Bypass Path Delay (Registered)

–

–

9.2

ns

7.4

0.1

8.5

2.0

6.3

6.1

6.8

5.1

6.4

47 ORP Delay

–

–

2.5

ns

48 ORP Bypass Delay

–

–

0.0

ns

2.0

0.0

24 I/O Register Setup Time before Clock

4.1

6.5

–

ns

–

25 I/O Register Hold Time after Clock

-0.6

-0.7

–

ns

–

26 I/O Register Clock to Out Delay

–

–

7.0

ns

6.0

27 I/O Register Reset to Out Delay

–

–

7.0

ns

6.0

28 Dedicated Input Delay

–

–

6.1

ns

4.3

30 GRP Delay, 4 GLB Loads

–

–

5.4

ns

31 GRP Delay, 8 GLB Loads

–

–

5.8

ns

32 GRP Delay, 16 GLB Loads

–

–

6.6

ns

33 GRP Delay, 48 GLB Loads

–

–

9.8

ns

3.7

4.1

4.8

7.5