1

High-Density Programmable Logic

Functional Block Diagram

Features

• HIGH DENSITY PROGRAMMABLE LOGIC

— 8,000 PLD Gates

— 96 I/O Pins, Twelve Dedicated Inputs

— 288 Registers

— High-Speed Global Interconnects

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Functionally and Pin-out Compatible to ispLSI 1048C

—

—

— TTL Compatible Inputs and Outputs

— Electrically Eraseable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispLSI DEVELOPMENT TOOLS

ispVHDL™ Systems

— VHDL/Verilog-HDL/Schematic Design Options

— Functional/Timing/VHDL Simulation Options

ispDS+™ VHDL Synthesis-Optimized Logic Fitter

— Supports Leading Third-Party Design Environments

for Schematic Capture, Synthesis and Timing

Simulation

— Static Timing Analyzer

ispDS™ Software

— Lattice HDL or Boolean Logic Entry

— Functional Simulator and Waveform Viewer

ISP Daisy Chain Download Software

Output Routing Pool

Output Routing Pool

F7 F6 F5 F4 F3 F2 F1 F0

B0 B1 B2 B3 B4 B5 B6 B7

A0

A1

A2

A3

A4

A5

A6

A7

Output Routing Pool

Output Routing Pool

CLK

E7 E6 E5 E4 E3 E2 E1 E0

C0 C1 C2 C3 C4 C5 C6 C7

D7

D6

D5

D4

D3

D2

D1

D0

Logic

Array

DQ

DQ

DQ

DQ

Global Routing Pool (GRP)

GLB

0139G1A-isp

Description

The ispLSI 1048E is a High-Density Programmable Logic

Device containing 288 Registers, 96 Universal I/O pins,

12 Dedicated Input pins, four Dedicated Clock Input pins,

two dedicated Global OE input pins, and a Global Routing

Pool (GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 1048E fea-

tures 5V in-system programmability and in-system

diagnostic capabilities. The ispLSI 1048E offers non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems. A

functional superset of the ispLSI 1048 architecture, the

ispLSI 1048E device adds two new global output enable

pins and two additional dedicated inputs.

The basic unit of logic on the ispLSI 1048E device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…F7 (see Figure 1). There are a total of 48 GLBs in the

ispLSI 1048E device. Each GLB has 18 inputs, a pro-

grammable AND/OR/Exclusive OR array, and four outputs

which can be configured to be either combinatorial or

registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any other GLB on the device.

1048E_08

Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

July 1998

Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com