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KH561AM Datasheet(PDF) 8 Page - Fairchild Semiconductor |
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KH561AM Datasheet(HTML) 8 Page - Fairchild Semiconductor |
8 / 13 page DATA SHEET KH561 8 REV. 1A February 2001 Figure 4: Voltage Gain Derivation Note again that if Ri = 0 this expression would simplify considerably. Also, if G were very large the voltage gain expression would reduce to the familiar non-inverting op amp gain equation. These two performance equations, shown below, provide a means to derive the design equa- tions for Rf and Rg given a desired no load gain and out- put impedance. Performance Equations Design Equations Equivalent Model Given that the physical feedback and gain setting resistors have been determined in accordance with the design equations shown above, an equivalent model may be created for the gain to the load where the amplifier block is taken as a standard op amp. Figure 5 shows this analysis model and the resulting gain equation to the load. Figure 5: Equivalent Model This model is used to generate the DC error and noise performance equations. As with any equivalent model, the primary intent is to match the external terminal characteristics recognizing that the model distorts the internal currents and voltages. In this case, the model would incorrectly predict the output pin voltage swing for a given swing at the load. But it does provide a simplified means of getting to the external terminal characteristics. External Compensation Capacitor (Cx) As shown in the test circuit of Figure 1, the KH561 requires an external compensation capacitor from the output to pin 19. The recommended values described here assume that a maximally flat frequency response into a matched load is desired. The required Cx varies widely with the desired value of output impedance and to a lesser degree on the desired gain. Note from Figure 2, the simplified internal schematic, that the actual total compensation (Ct) is the series combination of Cx and the internal 10pF from pin 19 to the compensation nodes. The total compensation (Ct) is developed in two steps as shown below. recognize that [taking V positive] V V Gi R solving for V from two directions VV i R G 1 i R solving for i from this i V G1 R R then VV VR G1 R R and, substituting for V and i in the original V expression VV 1 GR R i o err f i err i err g err err i gi i ii gi err o oi f =+ =− = + () = + () + =− + () + =+ − − − − − − ii gi f g v o i f g i f i g v f g i G1 R R pulling an R R out of the fraction A V V 1 R R G R R G1 R R note that A 1 R R G G1 R0 + () + ≡= + − ++ =+ + = R RR R R G R R A R R G R R G R R o f i f g i g v f g i f i g = ++ ++ =+ − ++ 1 1 1 1 RG R A R R RR A f ov i g f o v =+ () − = − − 1 1 Rg Vi RL Vo Ro Rf - Ro Classical op-amp + - V V 1 RR R R RR substituting in for R and R with their design equation yields V V A R RR A (gain to load) o i f o g L Lo f g o i v L Lo L =+ − + = + = C 300 R 1 2.0 R pF intermediate equation C C 1 0.02 C pF total compensation 1 og t 1 1 =− = + () |
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