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MAX1165CCUI Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAX1165CCUI Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 15 page external reference to REFADJ, the input impedance is typically 5k Ω. Using the buffered REFADJ input makes buffering the external reference unnecessary; however, the internal buffer output must be bypassed at REF with a 1µF capacitor. Connect REFADJ to AVDD to disable the internal buffer. Directly drive REF using an external reference. During conversion the external reference must be able to drive 100µA of DC load current and have an output imped- ance of 10 Ω or less. REFADJ’s impedance is typically 5k Ω. The DC input impedance of REF is a minimum 40k Ω. For optimal performance, buffer the reference through an op amp and bypass REF with a 1µF capacitor. Consider the MAX1165/MAX1166s’ equivalent input noise (38µVRMS) when choosing a reference. Reading a Conversion Result EOC is provided to flag the microprocessor when a con- version is complete. The falling edge of EOC signals that the data is valid and ready to be output to the bus. D0–D15 are the parallel outputs of the MAX1165/ MAX1166. These three-state outputs allow for direct connection to a microcontroller I/O bus. The outputs remain high-impedance during acquisition and conver- sion. Data is loaded onto the bus with the third falling edge of CS with R/C high after tDO. Bringing CS high forces the output bus back to high impedance. The MAX1165/MAX1166 then wait for the next falling edge of CS to start the next conversion cycle (Figure 2). The MAX1165 loads the conversion result onto a 16-bit wide data bus while the MAX1166 has a byte-wide out- put format. HBEN toggles the output between the most/least significant byte. The least significant byte is loaded onto the output bus when HBEN is low and the most significant byte is on the bus when HBEN is high (Figure 2). RESET Toggle RESET with CS high. The next falling edge of CS begins acquisition. This reset is an alternative to the dummy conversion explained in the Starting a Conversion section. Transfer Function Figure 8 shows the MAX1165/MAX1166 output transfer function. The output is coded in standard binary. Input Buffer Most applications require an input buffer amplifier to achieve 16-bit accuracy. If the input signal is multi- plexed, the input channel should be switched immedi- ately after acquisition, rather than near the end of or after a conversion. This allows more time for the input buffer amplifier to respond to a large step change in input signal. The input amplifier must have a high enough slew rate to complete the required output volt- age change before the beginning of the acquisition time. At the beginning of acquisition, the internal sam- pling capacitor array connects to AIN (the amplifier out- put), causing some output disturbance. Ensure that the sampled voltage has settled to within the required limits before the end of the acquisition time. If the frequency of interest is low, AIN can be bypassed with a large enough capacitor to charge the internal sampling capacitor with very little ripple. However, for AC use, AIN must be driven by a wideband buffer (at least 10MHz), which must be stable with the ADC’s capaci- tive load (in parallel with any AIN bypass capacitor used) and also settle quickly. An example of this circuit using the MAX4434 is given in Figure 9. Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface ______________________________________________________________________________________ 11 OUTPUT CODE FULL-SCALE TRANSITION 11...111 12 3 0 FS INPUT VOLTAGE (LSB) FS - 3/2LSB 11...110 11...101 00...011 00...010 00...001 00...000 FS = VREF 1LSB = VREF 65536 Figure 8. MAX1165/MAX1166 Transfer Function MAX1165 MAX1166 MAX4434 ANALOG INPUT 10 Ω AIN 40pF Figure 9. MAX1165/MAX1166 Fast Settling Input Buffer |
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