MC68HC812A4 datasheet(10/342 Pages) MOTOROLA

Part #	MC68HC812A4

Description	16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

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Manufacturer	MOTOROLA [Motorola, Inc]

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10 / 342 page

MC68HC812A4 — Rev. 3.0

Advance Information

10

Table of Contents

MOTOROLA

Table of Contents

Section 10. Clock Module

10.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

10.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

10.3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

10.3.1

Clock Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

10.4

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

10.5

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

10.5.1

Computer Operating Properly (COP) . . . . . . . . . . . . . . . . .156

10.5.2

Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

10.5.3

Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

10.5.4

Peripheral Clock Divider Chains. . . . . . . . . . . . . . . . . . . . .158

10.6

Registers and Reset Initialization . . . . . . . . . . . . . . . . . . . . . .161

10.6.1

Real-Time Interrupt Control Register . . . . . . . . . . . . . . . . .161

10.6.2

Real-Time Interrupt Flag Register . . . . . . . . . . . . . . . . . . .163

10.6.3

COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

10.6.4

Arm/Reset COP Timer Register . . . . . . . . . . . . . . . . . . . . .166

Section 11. Phase-Lock Loop (PLL)

11.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

11.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

11.3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

11.4

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

11.5

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

11.6

Registers and Reset Initialization . . . . . . . . . . . . . . . . . . . . . .171

11.6.1

Loop Divider Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

11.6.2

Reference Divider Registers . . . . . . . . . . . . . . . . . . . . . . .172

11.6.3

Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

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