IDT70V3319 datasheet(5/23 Pages) IDT

Part #	IDT70V3319

Description	HIGH-SPEED 3.3V 256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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5 / 23 page

6.42

IDT70V3319/99S

High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

5

Pin Names

Left Port

Right Port

Names

CE0L,

CE1L

CE0R,

CE1R

Chip Enables(6)

R/WL

R/WR

Read/Write Enable

OEL

OER

Output Enable

A0L - A17L(1)

A0R - A17R(1)

Address

I/O0L - I/O17L

I/O0R - I/O17R

Data Input/Output

CLKL

CLKR

Clock

PIPE/FTL(5)

PIPE/FTR(5)

Pipeline/Flow-Through

ADSL

ADSR

Address Strobe Enable

CNTENL

CNTENR

Counter Enable

REPEATL

REPEATR

Counter Repeat(4)

UBL

UBR

Upper Byte Enable (I/O9-I/O17)(6)

LBL

LBR

Lower Byte Enable (I/O0-I/O8)(6)

VDDQL

VDDQR

Power (I/O Bus) (3.3V or 2.5V)(2)

OPTL

OPTR

Option for selecting VDDQX(2,3)

VDD

Power (3.3V)(2)

VSS

Ground (0V)

TDI

Test Data Input

TDO

Test Data Output

TCK

Test Logic Clock (10MHz)

TMS

Test Mode Select

TRST

Reset (Initialize TAP Controller)

5623 tbl 01

1. A17 is a NC for IDT70V3399.

2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

3. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that

port's I/Os and address controls will operate at 2.5V levels and VDDQX must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

4. When REPEATX is asserted, the counter will reset to the last valid address loaded

via ADSX.

5. PIPE/FT option in PK-128 package is not supported due to limitation in pin count.

Device is pipelined output mode only on each port.

6. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the

signals take two cycles to deselect.

NOTES:

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