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70V7319S133BFGI8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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70V7319S133BFGI8 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 22 page ©2015 Integrated Device Technology, Inc. JUNE 2015 DSC 5629/10 1 Functional Block Diagram Features: ◆ 256K x 18 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 18 banks – 4 megabits of memory on chip ◆ Bank access controlled via bank address pins ◆ High-speed data access – Commercial:3.4ns(200MHz)/3.6ns(166MHz)/ 4.2ns (133MHz) (max.) – Industrial:3.6ns(166MHz)/4.2ns(133MHz)(max.) ◆ Selectable Pipelined or Flow-Through output mode ◆ Counter enable and repeat features ◆ Dual chip enables allow for depth expansion without additional logic ◆ Full synchronous operation on both ports – 5ns cycle time, 200MHz operation (14Gbps bandwidth) – Fast 3.4ns clock to data out – 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MH – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time ◆ Separate byte controls for multiplexed bus and bus match- ingcompatibility ◆ LVTTL- compatible, 3.3V (±150mV) power supply for core ◆ LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port ◆ Industrial temperature range (-40°C to +85°C) is available at 166MHz and 133MHz ◆ Available in a 208-pin fine pitch Ball Grid Array (fpBGA) and 256-pin Ball Grid Array (BGA) ◆ Supports JTAG features compliant with IEEE 1149.1 ◆ Green parts available, see ordering information HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V7319S 4Kx18 MEMORY ARRAY (BANK 63) MUX MUX PL/ FTL OPTL CLKL ADSL CNTENL REPEATL R/ WL CE0L CE1L UBL LBL OEL I/O0L-17L A11L A0L JTAG 4Kx18 MEMORY ARRAY (BANK 1) MUX MUX 4Kx18 MEMORY ARRAY (BANK 0) MUX MUX CONTROL LOGIC I/O CONTROL BANK DECODE ADDRESS DECODE I/O0R-17R A11R A0R CONTROL LOGIC I/O CONTROL BANK DECODE ADDRESS DECODE 5629 drw 01 BA5R BA4R BA3R BA2R BA1R BA0R BA5L BA4L BA3L BA2L BA1L BA0L , PL/ FTR OPTR CLKR ADSR CNTENR REPEATR R/ WR CE0R CE1R UBR LBR OER TMS TCK TRST TDI TDO NOTE: 1. TheBank-Switchabledual-portusesatrueSRAMcore insteadofthetraditionaldual-portSRAMcore.Asaresult,it hasuniqueoperatingcharacteristics.Pleaserefertothe functionaldescriptiononpage19fordetails. |
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