70V3579S5DRG8 datasheet(6/17 Pages) IDT

Part #	70V3579S5DRG8

Description	HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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Manufacturer	IDT [Integrated Device Technology]

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6.42

IDT70V3579S

High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

6

Recommended Operating

Temperature and Supply Voltage(1)

Recommended DC Operating

Conditions with VDDQ at 2.5V

Absolute Maximum Ratings(1)

Truth Table II—Address Counter Control(1,2)

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.

3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.

4. ADS and CNTRST are independent of all other memory control signals including CE0, CE1 and BEn

5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.

NOTES:

1. VIL > -1.5V for pulse width less than 10 ns.

2. VTERM must not exceed VDDQ + 125mV.

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to VIL(0V), and VDDQX for that port must be supplied

as indicated above.

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or 4ns

maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.

NOTE:

1. Industrial temperature: for specific speeds, packages and powers contact your

sales office.

Address

Addr

Used

CLK(6)

ADS

CNTEN

CNTRST

I/O(3)

MODE

XX

0

↑

XX

L(4)

DI/O(0)

Counter Reset to Address 0

An

X

An

↑

L(4)

XH

DI/O (n)

External Address Used

An

Ap

↑

HH

H

DI/O(p)

External Address Blocked—Counter disabled (Ap reused)

XAp

Ap + 1

↑

H

L(5)

HDI/O(p+1) Counter Enabled—Internal Address generation

4830 tbl 03

Grade

Ambient

Temperature

GND

VDD

Commercial

0OC to +70OC0V

3.3V

+ 150mV

Industrial

-40OC to +85OC0V

3.3V

+ 150mV

4830 tbl 04

Symbol

Parameter

Min.

Typ.

Max.

Unit

VDD

Core Supply Voltage

3.15

3.3

3.45

V

VDDQ

I/O Supply Voltage(3)

2.375

2.5

2.625

V

VSS

Ground

0

V

VIH

Input High Voltage(3)

(Address & Control Inputs)

1.7

____

VDDQ + 125mV(2)

V

VIH

Input High Voltage - I/O(3)

1.7

____

VDDQ + 125mV(2)

V

VIL

Input Low Voltage

-0.3(1)

____

0.7

V

4830 tbl 05a

Symbol

Rating

Commercial

& Industrial

Unit

VTERM(2)

Terminal Voltage

with Respect to

GND

-0.5 to +4.6

V

TBIAS

Temperature

Under Bias

-55 to +125

o

C

TSTG

Storage

Temperature

-65 to +150

o

C

IOUT

DC Output Current

50

mA

4830 tbl 06

Recommended DC Operating

Conditions with VDDQ at 3.3V

NOTES:

1. VIL > -1.5V for pulse width less than 10 ns.

2. VTERM must not exceed VDDQ + 150mV.

3. To select operation at 3.3V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be

supplied as indicated above.

Symbol

Parameter

Min.

Typ.

Max.

Unit

VDD

Core Supply Voltage

3.15

3.3

3.45

V

VDDQ

I/O Supply Voltage(3)

3.15

3.3

3.45

V

VSS

Ground

0

V

VIH

Input High Voltage

(Address & Control Inputs)(3)

2.0

____

VDDQ + 150mV(2)

V

VIH

Input High Voltage - I/O(3)

2.0

____

VDDQ + 150mV(2)

V

VIL

Input Low Voltage

-0.3(1)

____

0.8

V

4830 tbl 05b

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