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70V3579S6DRG8 Datasheet(PDF) 5 Page - Integrated Device Technology |
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70V3579S6DRG8 Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 17 page  6.42 IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges 5 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. 4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here. Truth Table I—Read/Write and Enable Control(1,2,3,4) Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A14L A0R - A14R Address I/O0L - I/O35L I/O0R - I/O35R Data Input/Output CLKL CLKR Clock ADSL ADSR Address Strobe Enable CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset BE0L - BE3L BE0R - BE3R Byte Enables (9-bit bytes) VDDQL VDDQR Power (I/O Bus) (3.3V or 2.5V)(1) OPTL OPTR Option for selecting VDDQX(1,2) VDD Power (3.3V)(1) VSS Ground (0V) 4830 tbl 01 OE CLK CE0 CE1 BE3 BE2 BE1 BE0 R/W Byte 3 I/O27-35 Byte 2 I/O18-26 Byte 1 I/O9-17 Byte 0 I/O0-8 MODE X ↑ H X XXXXX High-Z High-Z High-Z High-Z Deselected–Power Down X ↑ X L XXXXX High-Z High-Z High-Z High-Z Deselected–Power Down X ↑ L H H H H H X High-Z High-Z High-Z High-Z All Bytes Deselected X ↑ L H H H H L L High-Z High-Z High-Z DIN Write to Byte 0 Only X ↑ LH H H LH L High-Z High-Z DIN High-Z Write to Byte 1 Only X ↑ LH H L H H L High-Z DIN High-Z High-Z Write to Byte 2 Only X ↑ LH LH H H L DIN High-Z High-Z High-Z Write to Byte 3 Only X ↑ L H H H L L L High-Z High-Z DIN DIN Write to Lower 2 Bytes Only X ↑ LH L L H H L DIN DIN High-Z High-Z Write to Upper 2 bytes Only X ↑ L H LLLLL DIN DIN DIN DIN Write to All Bytes L ↑ L H H H H L H High-Z High-Z High-Z DOUT Read Byte 0 Only L ↑ LH H H LH H High-Z High-Z DOUT High-Z Read Byte 1 Only L ↑ LH H L H H H High-Z DOUT High-Z High-Z Read Byte 2 Only L ↑ LH LH H H H DOUT High-Z High-Z High-Z Read Byte 3 Only L ↑ LH H H L L H High-Z High-Z DOUT DOUT Read Lower 2 Bytes Only L ↑ LH L L H H H DOUT DOUT High-Z High-Z Read Upper 2 Bytes Only L ↑ L H LLLL H DOUT DOUT DOUT DOUT Read All Bytes H ↑ L H LLLL X High-Z High-Z High-Z High-Z Outputs Disabled 4830 tbl 02 NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2. OPTX selects the operating voltage levels on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. |
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