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70V9089S15PFGI8 Datasheet(PDF) 10 Page - Integrated Device Technology |
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70V9089S15PFGI8 Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 19 page 6.42 IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges 10 An An + 1 An + 2 An + 3 tCYC2 tCH2 tCL2 R/ W ADDRESS CE0 CLK CE1 (4) DATAOUT OE tCD2 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE 3750 drw 07 (1) (1) (1) (2) tSC tHC tSW tHW tSA tHA tDC tSC tHC (5) (1 Latency) Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL)(3,6) Timing Waveform of Read Cycle for Pipelined Output (FT/PIPE"X" = VIH)(3,6) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL and CNTRST = VIH. 4. The output is disabled (High-impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. "x" denotes Left or Right port. The diagram is with respect to that port. An An + 1 An + 2 An + 3 tCYC1 tCH1 tCL1 R/ W ADDRESS DATAOUT CE0 CLK OE tSC tHC tCD1 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE tCKHZ 3750 drw 06 (1) (1) (1) (1) (2) CE1 (4) tSW tHW tSA tHA tDC tDC (5) tSC tHC |
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