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709149S8PFGI8 Datasheet(PDF) 9 Page - Integrated Device Technology |
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709149S8PFGI8 Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 10 page 6.42 IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges 9 Truth Table II: Clock Enable Function Table(1) Truth Table I: Read/Write Control(1) Functional Description The IDT709149 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide very short set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. The internal write pulse width is dependent only on the low to high transitions of the clock signal to initiate a write allowing the shortest possible realized cycle times. Clock enable inputs are provided to stall the operation of the address and data input registers without introduc- ing clock skew for very fast interleaved memory applications. A HIGH on the CE input for one clock cycle will power down the internal circuitry to reduce static power consumption. When piplelined mode is enabled, two cycles are required with CE LOW to reactivate the outputs. NOTES: 1. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'L' = LOW voltage level steady state 'l' = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'X' = Don't care, 'NC' = No change 2. CLKEN = VIL must be clocked in during Power-Up. 3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are LOW, a write cycle is initiated on the LOW- to-HIGH transition of the CLK. Termination of a write cycle is done on the next LOW-to-HIGH transistion of the CLK. 4. The register outputs are internal signals from the register inputs being clocked in or disabled by CLKEN. Inputs Outputs Mode Synchronous(3) Asynchronous CLK CE R/W OE I/O0-8 ↑ H X X High-Z Deselected—Power Down ↑ LL X DATAIN Selected and Write Enable ↑ LH L DATAOUT Read Selected and Data Output Enabled Read (1 Latency) ↑ X X H High-Z Data I/O Disabled 3494 tbl 09 Inputs Register Inputs Register Outputs(4) Operating Mode CLK(3) CLKEN(2) ADDR DATAIN ADDR DATAOUT Load "1" ↑ LH H H H Load "0" ↑ LLLLL Hold (do nothing) ↑ HX X NC NC X H X X NC NC 3494 tbl 10 |
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